1. Field of the Invention
The present invention relates to integrated circuit testing and, in particular, to a scan flip-flop that holds state during scan mode, thereby allowing robust delay path tests to be developed using combinational automatic test pattern generation (ATPG).
2. Discussion of the Related Art
One method of testing integrated circuit devices for silicon defects is to generate ATPG vectors using both the stuck at fault model and the delay path fault model. The ATPG algorithms generally assume the circuit design to be combinational in nature. To aid the ATPG tool in this effort, some or all of the flip-flops in the circuit design are converted to scan flip-flops. These scan flops are stitched into one or more shift registers known as scan chains. This makes every scan flip-flop output a primary input and every scan flip-flop input a primary output.
As shown in FIG. 1, a standard scan flip-flop is a normal flip-flop 10 with a multiplexer (mux) 12 at the input of a master latch 14. The mux 12 is under the control of a test enable signal (TEZ). When TEZ is high (inactive), the mux 12 selects the D (normal data) input. When TEZ is low (active), the mux 12 selects the SD (scan data) input. This connects all the scan flip-flops in the scan chain into a shift register, the SD input of each flip-flop in the chain being connected to receive the Q or QZ output of the slave latch 16 of the previous flip-flop in the chain.
The protocol for applying ATPG vectors using scan chains is as follows. The values that the ATPG algorithm needs to apply to the device under test are shifted into the scan chains. The last clock cycle of this shift mode operation is known as the launch clock. The value at the Q outputs of the flip-flops in the scan chain after the launch clock are the values to be applied by the ATPG algorithm to the inputs of the combinational logic under test. Thus, the Q outputs of all scan flops can be considered primary inputs to the logic block under test. When TEZ goes high, the mux 12 selects the normal data input D instead of SD. This allows the logic value at D to be captured. Since the outputs of the combinational logic block under test are connected to D, the D inputs of the scan flops are used as primary outputs for the logic block under test.
The delay path fault model is used to test for circuit defects that cause an increase in the delay of a datapath in the device under test. Non-robust delay path testing considers a path tested if all on-path nodes undergo a steady state transition. No constraints are placed on off-path inputs. A problem with this model is that a different path than the targeted path might be tested. If this path is shorter, then the test may allow a defect to escape undetected. A robust delay path test considers a path tested if all on-path nodes undergo a steady state transition and all off-path inputs are held steady. This insures that the targeted path is tested. 100% robust delay path coverage of a selected faultlist is possible only with a scan flip-flop that can hold the state of the slave latch during shift mode.
U.S. Pat. No. 5,015,875, issued May 14, 1991, to Giles et al., provides an example of a scan flip-flop for use in a test mode scan operation. The Giles et al. flip-flop has the capability of not toggling its parallel output during the scan operation. It uses a master latch, which is controlled by a scan multiplexer, to update a slave latch having two alternate slave latch portions. Switching logic determines which of the alternate slave latches is updated with the incoming data signal. The normal test enable signal controls the switching logic. Therefore, the design requires no additional control signals.
During scan mode operation, data is clocked through the Giles et al. flip-flop from a scan-data-in terminal and out the scan-data-out terminal of one of the alternate slave latch portions without affecting the system data output Q of the other alternate slave latch portion. The shift sequence is followed by a capture interval during which the Q output is automatically updated with the desired data to test the targeted path. Thus, the path under test is not affected by the loading of the ATPG vector.